The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for minimizing power consumption for fixed-frequency processing unit operation.
Oftentimes, central processing unit (CPU) design focuses on one or more of datapaths, control units, memory components, clock circuitry, pad transceiver circuitry, logic gate cell libraries, or the like. CPUs designed for high-performance markets may require custom designs for each of these items to achieve a desired frequency, power-dissipation, chip-area goal, or the like. Therefore, a CPU design project generally comprises major tasks, such as: programmer-visible instruction set architecture, architectural study and performance modeling, high-level synthesis or logic implementation, circuit design of speed critical components, logic synthesis or logic-gate-level design, chip timing analysis to confirm that all logic and circuits will run at a specified operating frequency, physical design, as well as other design specifications.
Specific to chip timing is a nominal chip frequency, which is chosen based on worst-case corners often with large guard bands. Worst-case corners refer to all worst case conditions within a chip, such as highest possible temperature, worst possible workload, or the like. Large guard bands refers to additional voltage added for a given frequency of operation or a reduction in frequency for a given voltage to move away from an operational point where a chip timing failure has been demonstrated or projected to occur under some selected temperature and workload conditions. However, current technology is limited in reducing these large guard bands for chips with fully synchronous clocking grids. Further, for chips with asynchronous clocking grids, while guard bands may be reduced using dynamic frequency adjustments, these adjustments may not be made when the system bus frequency is equal to the core frequency, i.e. fixed frequencies.